According to TrendForce's Monitoring, Huawei's semiconductor chief He Tingbo published the paper "Time Microscaling Theory for Multilevel Electronic Systems" (Taofu Law) V2 on July 3rd on ChinaXiv, the preprint platform of the Chinese Academy of Sciences. Compared to the V1 version released on May 25th, the new version supplements a large amount of engineering implementation details and empirical quantified data based on the theoretical framework, forming an 8-chapter complete exposition system. It also adds principles and physical schematic diagrams covering core technologies such as the τ-level spatiotemporal model, LogicFolding architecture, bonding interface cross-section, Unified Bus interconnect architecture, and Hi-ONE optical engine.

At the engineering implementation level, the V2 version elaborates deeply on the "Gear Ratio" concept of LogicFolding: when the hybrid bonding pitch approaches the top-layer metal wiring size, the 3D design space shifts from traditional "macroblock-level discrete optimization" to "unit-level continuous optimization." This can achieve globally optimal vertical logic partitioning, breaking through the limitation of traditional 3D stacking that can only layer by functional blocks. The V2 version also provides mass-produced measured data tables for the first time, clearly listing the voltage, frequency, normalized power consumption, area, and power density parameters of Kirin 2026 and the reference Kirin 9030 Pro. This further validates through measurements the post-Moore's Law scaling theory centered on the time constant τ.

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